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digital power monitor with clear pin and alert output adm1192 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features powered from 3.15 v to 26 v precision current sense amplifier precision voltage input 12-bit adc for current and voltage readback alert output allows basic p-channel fet hot swap up to 26 v setv input for setting overcurrent alert threshold programmable overcurrent filtering via timer pin clrb input pin i 2 c? fast mode-compliant interface (400 khz maximum) 10-lead msop applications power monitoring/power budgeting central office equipment telecommunication and data communication equipment pcs/servers general description the adm1192 is an integrated current sense amplifier that offers digital current and voltage monitoring via an on-chip, 12-bit analog-to-digital conv erter (adc), communicated through an i 2 c interface. an internal current sense amplifier senses voltage across the sense resistor in the power path via the vcc pin and the sense pin. a 12-bit adc can measure the current seen in the sense resistor and in the supply voltage on the vcc pin. an industry-standard i 2 c interface allows a controller to read current and voltage data from the adc. measurements can be initiated by an i 2 c command. alternatively, the adc can run continuously, and the user can read the latest conversion data whenever it is required. up to four unique i 2 c addresses can be created, depending on the way the adr pin is connected. a setv pin is also included. a voltage applied to this pin is internally compared to the output voltage on the current sense amplifier. the output of the setv comparator asserts when the current sense amplifier output exceeds the setv voltage. this event is detected at the alert block. the alert block then charges up the external timer capacitor with a fixed current. when this timing cycle is complete, the alert output asserts. functional block diagram v i 0 1 adm1192 sense setv vcc mux i 2 c alert clrb current sense amplifier a sda scl adr alert gnd timer 05754-001 comparator 12-bit adc figure 1. r sense p = vi controller adm1192 sense vcc sda scl sda scl gnd alert clrb clrb adr timer 3.15v to 26 v setv alert 05754-013 figure 2. applications diagram the alert output can be used as a flag to warn a micro- controller or field programmable gate array (fpga) of an overcurrent condition. alert outputs of multiple adm1192 devices can be tied together and used as a combined alert. a basic p-channel fet hot swap circuit can be implemented with the alert output. the value of the timer capacitor should be set so that the charging time of this capacitor is much longer than the period where a higher than nominal inrush current may be flowing. the adm1192 is packaged in a 10-lead msop.
adm1192 rev. 0 | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 5 thermal characteristics .............................................................. 5 esd caution.................................................................................. 5 pin configuration and function descriptions............................. 6 typical performance characteristics ............................................. 7 voltage and current readback ..................................................... 10 serial bus interface..................................................................... 10 identifying the adm1192 on the i 2 c bus............................... 10 general i 2 c timing.................................................................... 10 timing diagrams ....................................................................... 11 write and read operations ...................................................... 12 quick command........................................................................ 12 write command byte ................................................................ 12 write extended byte .................................................................. 13 read voltage and/or current data bytes ................................ 14 alert output............................................................................ 15 setv pin ..................................................................................... 15 kelvin sense resistor connection ........................................... 16 outline dimensions ....................................................................... 17 ordering guide .......................................................................... 17 revision history 9/06revision 0: initial version
adm1192 rev. 0 | page 3 of 20 specifications v cc = 3.15 v to 26 v; t a = ?40c to +85c; typical values at t a = 25c, unless otherwise noted. table 1. parameter min typ max unit conditions vcc pin operating voltage range, v vcc 3.15 26 v supply current, i cc 1.7 2 ma undervoltage lockout, v uvlo 2.8 v v cc rising undervoltage lockout hysteresis, v uvlohyst 80 mv monitoring accuracy 1 current sense absolute accuracy ?1.45 +1.45 % v sense = 75 mv 0c to +70c ?1.8 +1.8 % v sense = 50 mv 0c to +70c ?2.8 +2.8 % v sense = 25 mv 0c to +70c ?5.7 +5.7 % v sense = 12.5 mv 0c to +70c ?1.5 +1.5 % v sense = 75 mv 0c to +85c ?1.8 +1.8 % v sense = 50 mv 0c to +85c ?2.95 +2.95 % v sense = 25 mv 0c to +85c ?6.1 +6.1 % v sense = 12.5 mv 0c to +85c ?1.95 +1.95 % v sense = 75 mv ?40c to +85c ?2.45 +2.45 % v sense = 50 mv ?40c to +85c ?3.85 +3.85 % v sense = 25 mv ?40c to +85c ?6.7 +6.7 % v sense = 12.5 mv ?40c to +85c v sense for adc full scale 105.84 mv this is an absolute value to be used when converting adc codes to current readings; any inaccuracy in this value is factored into absolute current accuracy values (see specs for current sense absolute accuracy) voltage sense accuracy ?0.85 +0.85 % v vcc = 3.0 v to 5.5 v (low range) 0c to +70c ?0.9 +0.9 % v vcc = 10.8 v to 16.5 v (high range) 0c to +70c ?0.85 +0.85 % v vcc = 3.0 v to 5.5 v (low range) 0c to +85c ?0.9 +0.9 % v vcc = 10.8 v to 16.5 v (high range) 0c to +85c ?0.9 +0.9 % v vcc = 3.0 v to 5.5 v (low range) ?40c to +85c ?1.15 +1.15 % v vcc = 10.8 v to 16.5 v (high range) ?40c to +85c v cc for adc full scale, low range (vrange = 1) 6.65 v v cc for adc full scale, high range (vrange = 0) 26.52 v these are absolute values to be used when converting adc codes to voltage readings; any inaccuracy in these values is factored into voltage accuracy values (see specs for voltage accuracy) clrb pin logic low threshold, v clrbl 0.8 v input current for logic low input, i clrbl ?40 ?22 a v clrb = 0 v to 0.8 v logic high threshold, v clrbh 1.6 mv input current for logic high input, i clrbh 3 6 a v clrb = 1.6 v to 5.5 v sense pin input current, i sense ?1 +1 a v sense = v vcc
adm1192 rev. 0 | page 4 of 20 parameter min typ max unit conditions setv pin overcurrent trip threshold 98 100 102 mv v setv = 1.8 v 49.5 50 50.5 mv v setv = 0.9 v overcurrent trip, gain {v setv /(v vcc ? v sense )} 18 v setv = 0.9 v to 1.9 v input current, i setvleak ?1 +1 a v setv = 0.9 v to 1.9 v glitch filter, t setvglitch 3 s timer pin pull-up current (overcurrent fault), i timerupoc ?46 ?62 ?78 a (18.125 v sense ) > v setv , v timer = 1 v pull-down current, i timerdn 100 a normal operation, v timer = 1 v pin threshold high, v timerh 1.275 1.3 1.325 v timer rising alert pin output low voltage, v alertol 0.05 0.1 v i alert = ?100 a 1 1.5 ma i alert = ?2 ma input current, i alert ?1 +1 a v alert = v cc ; alert asserted adr pin set address to 00, v adrlowv 0 0.8 v low state set address to 01, r adrlowz 80 120 160 k resistor to ground state, load pin with specified resistance for 01 decode set address to 10, i adrhighz ?0.3 +0.3 a open state, maximum load allowed on adr pin for 10 decode set address to 11, v adrhighv 2 5.5 v high state input current for 00 decode, i adrlow 3 6 a v adr = 2.0 v to 5.5 v input current for 11 decode, i adrhigh ?40 ?25 a v adr = 0 v to 0.8 v i 2 c timing low level input voltage, v il 0.3 v bus v high level input voltage, v ih 0.7 v bus v low level output voltage on sda, v ol 0.4 v i ol = 3 ma output fall time on sda from v ihmin to v ilmax 20 + 0.1 c b 250 ns c b = bus capacitance from sda to gnd maximum width of spikes suppressed by input filtering on sda and scl pins 50 250 ns input current, i i , on sda/scl when not driving out a logic low ?10 +10 a input capacitance on sda/scl 5 pf scl clock frequency, f scl 400 khz low period of the scl clock 600 ns high period of the scl clock 1300 ns setup time for repeated start condition, t su;sta 600 ns sda output data hold time, t hd;dat 100 900 ns setup time for a stop condition, t su;sto 600 ns bus free time between a stop and a start condition, t buf 1300 ns capacitive load for each bus line 400 pf 1 monitoring accuracy is a measure of the er ror in a code that is read back for a pa rticular voltage/current. this is a combinat ion of amplifier error, reference error, adc error, and error in adc full-scale code conversion factor.
adm1192 rev. 0 | page 5 of 20 absolute maximum ratings table 2. parameter rating vcc pin 30 v sense pin 30 v timer pin ?0.3 v to +6 v clrb pin ?0.3 v to +6 v setv pin 30 v alert pin 30 v sda pin, scl pin ?0.3 v to +6 v adr pin ?0.3 v to +6 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c lead temperature (soldering 10 sec) 300c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. table 3. thermal resistance package type ja unit 10-lead msop 137.5 c/w esd caution
adm1192 rev. 0 | page 6 of 20 pin configuration and fu nction descriptions vcc 1 sense 2 setv 3 gnd 4 timer 5 alert 10 clrb 9 adr 8 sda 7 scl 6 a dm1192arm top view (not to scale) 05754-003 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 vcc positive supply input pin. the operating supply voltage range is 3.15 v to 26 v. an undervoltage lockout (uvlo) circuit resets the adm1192 when a low supply voltage is detected. 2 sense current sense input pin. a sense resistor between the vcc pin and the sense pin generates a voltage across a sense resistor. this voltage is proportional to the load current. a current sense amplifier amplifies this voltage before it is digitized by the adc. 3 setv input pin. the voltage driven onto this pin is compared to the output of the internal current sense amplifier. the lower the voltage on the setv, the lower the curr ent level that causes the alert output to assert. 4 gnd chip ground pin. 5 timer timer input pin. an external capacitor, c timer , sets the timing period for masking overcurrent conditions. this timing period should be sufficient to allow the load ch arge up completely with maximum current at startup without tripping an overcurrent fault. 6 scl i 2 c clock pin. open-drain input; requires an external resistive pull-up. 7 sda i 2 c data i/o pin. open-drain input/output; requires an external resistive pull-up. 8 adr i 2 c address pin. this pin can be tied low, tied high, left floating, or tied low through a resistor to set four different i 2 c addresses. 9 clrb clear pin. a latched overcurrent condition can be cleared by pulling this pin low. 10 alert alert output pin. active high, open-drain configuration. this pin asserts high when an overcurrent condition is present. the level at which an overcurrent conditio n is detected depends on the voltage on the setv pin.
adm1192 rev. 0 | page 7 of 20 typical performance characteristics 05754-021 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 4 8 12 16 20 24 28 i cc (ma) v cc (v) figure 4. supply current vs. supply voltage 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 80 60 40 20 0 ?20 i cc (ma) temperature (c) 05754-022 figure 5. supply current vs. temperature 05754-026 3.2 3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 v adr i adr (a) 11 decode 10 decode 01 decode 00 decode figure 6. address pin voltag e vs. address pin current for four addressing options 0 1000 900 800 700 600 500 400 300 200 100 hits per code (1000 reads) code 05754-060 2047 2048 2049 2050 2046 figure 7. adc noise, current channel, midcode input, 1000 reads 0 1000 900 800 700 600 500 400 300 200 100 hits per code (1000 reads) code 05754-061 780 781 782 783 779 figure 8. adc noise, 14:1 voltage channel, 5 v input, 1000 reads 0 1000 900 800 700 600 500 400 300 200 100 hits per code (1000 reads) code 05754-062 3079 3080 3081 3082 3078 figure 9. adc noise, 7:1 voltage channel, 5 v input, 1000 reads
adm1192 rev. 0 | page 8 of 20 4 3 2 1 0 ?1 ?2 ?3 ?4 0 4000 2500 3000 3500 2000 1500 1000 500 inl (lsb) code 05754-023 figure 10. inl for adc 4 3 2 1 0 ?1 ?2 ?3 ?4 0 4000 2500 3000 3500 2000 1500 1000 500 dnl (lsb) code 05754-024 figure 11. dnl for adc 0 100 80 90 70 60 50 40 30 20 10 02 . 0 1.8 1.6 1.41.21.00.80.60.40.2 v lim (mv) v setv (v) 05754-046 figure 12. v lim vs. v setv 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 ?40 80 60 40 20 0 ?20 alert low (v) temperature (c) 05754-047 figure 13. alert output low voltage vs. temperature @ 1 ma 05754-048 0 1.0 0.8 0.6 0.4 0.2 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 output low (v) v cc (v) figure 14. alert output low voltage vs. supply @ 1 ma 0 2.0 1.6 1.2 0.8 0.4 1.8 1.4 1.0 0.6 0.2 03 . 0 2.82.62.42.22.0 1.81.6 1.41.21.00.80.60.40.2 output low (v) load current (ma) 05754-049 figure 15. alert output low voltage vs. load current
adm1192 rev. 0 | page 9 of 20 2422201816141210 86 32 232119 17 151311 975 timer threshold (v) v cc (v) 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 42 6 5 high 05754-038 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?40 80 high 60 40 20 0 ?20 timer high threshold (v) temperature (c) 05754-039 figure 16. timer threshold vs. supply voltage figure 17. timer threshold vs. temperature
adm1192 rev. 0 | page 10 of 20 voltage and current readback the adm1192 contains the components to allow voltage and current readback over an inter-ic (i 2 c) bus. the voltage output of the current sense amplifier and the voltage on the vcc pin are fed into a 12-bit adc via a multiplexer. the device can be instructed to convert voltage and/or current at any time during operation via an i 2 c command. when all conversions are complete, the voltage and/or current values can be read out to 12-bit accuracy in two or three bytes. serial bus interface control of the adm1192 is carried out via the serial system management bus (i 2 c). this interface is compatible with i 2 c fast mode (400 khz maximum). the adm1192 is connected to this bus as a slave device, under the control of a master device. identifying the adm1192 on the i 2 c bus the adm1192 has a 7-bit serial bus slave address. when the device powers up, it does so with a default serial bus address. the five msbs of the address are set to 01011; the two lsbs are determined by the state of the adr pin. there are four different configurations available on the adr pin that correspond to four different i 2 c addresses for the two lsbs (see table 5 ). this scheme allows four adm1192 devices to operate on a single i 2 c. table 5. setting i 2 c addresses via the adr pin adr configuration address low state 0x68 resistor to gnd 0x69 floating (unconnected) 0x6a high state 0x6b general i 2 c timing figure 18 and figure 19 show timing diagrams for general read and write operations using the i 2 c. the i 2 c specification defines conditions for different types of read and write operations, which are discussed later. the general i 2 c protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, sda, while the serial clock line, scl, remains high. this indicates that a data stream follows. all slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit slave address (msb first) plus an r/ w bit that determines the direction of the data transfer; that is, whether data is written to or read from the slave device (0 = write, 1 = read). the peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the acknowledge bit, and holding it low during the high period of this clock pulse. all other devices on the bus now remain idle while the selected device waits for data to be read from it or written to it. if the r/ w bit is 0, the master writes to the slave device. if the r/ w bit is 1, the master reads from the slave device. 2. data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period because a low-to- high transition when the clock is high can be interpreted as a stop signal. if the operation is a write operation, the first data byte after the slave address is a command byte. this tells the slave device what to expect next. it can be an instruction, such as telling the slave device to expect a block write, or it can be a register address that tells the slave where subse- quent data is to be written. because data can flow in only one direction, as defined by the r/ w bit, it is not possible to send a command to a slave device during a read operation. before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read. 3. when all data bytes have been read or written, stop conditions are established. in write mode, the master pulls the data line high during the 10th clock pulse to assert a stop condition. in read mode, the master device releases the sda line during the low period before the ninth clock pulse, but the slave device does not pull it low. this is known as a no acknowledge. the master then takes the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a stop condition.
adm1192 rev. 0 | page 11 of 20 timing diagrams scl sda start by master 1 9 1 9 a1 a0 r/w 1 d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 0 acknowledge by slave acknowledge by slave acknowledge by slave acknowledge by slave frame 1 slave address frame 2 command code scl (continued) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 stop by master sda (continued) frame 3 data byte frame n data byte 05754-004 figure 18. general i 2 c write timing diagram scl sda start by master 1 9 1 9 a1 a0 r/w 1 d7 d6 d5 d4 d3 d2 d1 d0 1 1 0 0 acknowledge by slave acknowledge by master no acknowledge acknowledge by master frame 1 slave address frame 2 data byte scl (continued) d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 9 1 9 stop by master sda (continued) frame 3 data byte frame n data byte 05754-005 figure 19. general i 2 c read timing diagram sclscl sda p s t hd;sta t hd;dat t high t su;dat t su;sta t hd;sta t f t r t low t buf t su;sto p s 05754-006 figure 20. serial bus timing diagram
adm1192 rev. 0 | page 12 of 20 write and read operations the i 2 c specification defines several protocols for different types of read and write operations. the operations used in the adm1192 are discussed in the sections that follow. table 6 shows the abbreviations used in the command diagrams. table 6. i 2 c abbreviations abbreviation condition s start p stop r read w write a acknowledge n no acknowledge quick command the quick command operation allows the master to check if the slave is present on the bus, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address, followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. s slave address wa 12 3 05754-007 figure 21. quick command write command byte in the write command byte operation, the master device sends a command byte to the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address, followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends the command byte. the command byte is identified by an msb = 0. an msb =1 indicates an extended register write (see the write extended byte section). 5. the slave asserts an acknowledge on sda. 6. the master asserts a stop condition on sda to end the transaction. s slave address wa command byte ap 12 3 456 05754-008 figure 22. write command byte the seven lsbs of the command byte are used to configure and control the adm1192. table 7 provides details of the function of each bit. table 7. command byte operations bit default name function c0 0 v_cont set to convert voltage continuously. if readback is attempted before the first conversion is complete, the adm1192 asserts an acknowledge and returns all 0s in the returned data. c1 0 v_once set to convert voltage once. self-clears. i 2 c asserts a no acknowledge on attempted reads until adc conversion is complete. c2 0 i_cont set to convert voltage continuously. if readback is attempted before the first conversion is complete, the adm1192 asserts an acknowledge and returns all 0s in the returned data. c3 0 i_once set to convert current once. self-clears. i 2 c asserts a no acknowledge on attempted reads until adc conversion is complete. c4 0 vrange selects different internal attenuation resistor networks for voltage readback. a 0 in c4 selects a 14:1 voltage divider. a 1 in c4 selects a 7:2 voltage divider. with an adc full scale of 1.902 v, the voltage at the vcc pin for an adc full-scale result is 26.52 v for vrange = 0 and 6.65 v for vrange = 1. c5 0 n/a unused. c6 0 status_rd status read. when this bit is set, the data byte read back from the adm1192 is the status byte. this contains the status of the device alerts. see table 15 for full details of the status byte.
adm1192 rev. 0 | page 13 of 20 write extended byte in the write extended byte operation, the master device writes to one of the three extended registers of the slave device, as follows: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address, followed by the write bit (low). 3. the addressed slave device asserts an acknowledge on sda. 4. the master sends the register address byte. the msb of this byte is set to 1 to indicate an extended register write. the two lsbs indicate which of the three extended registers are to be written to (see table 8). all other bits should be set to 0. 5. the slave asserts an acknowledge on sda. 6. the master sends the command byte. the command byte is identified by an msb = 0. an msb = 1 indicates an extended register write. 7. the slave asserts an acknowledge on sda. 8. the master asserts a stop condition on sda to end the transaction. s slave address wa register address ap register data a 12 34 56 78 05754-009 figure 23. write extended byte table 9, table 1 0, and table 11 g ive det ai ls of e ach ex te nd e d register. table 8. extended register addresses a6 a5 a4 a3 a2 a1 a0 extended register 0 0 0 0 0 0 1 alert_en 0 0 0 0 0 1 0 alert_th 0 0 0 0 0 1 1 control table 9. alert_en register operations bit default name function 0 0 en_adc_oc1 enabled if a single adc conversion on the i chan nel has exceeded the threshold set in the alert_th register. 1 0 en_adc_oc4 enabled if four consecutive adc conversions on the i channel have exceeded the threshold set in the alert_th register. 2 1 en_oc_alert enables the oc_alert register. if an overcurrent cond ition is present and the timer pin has charged to 1.3 v, the oc_alert register cap tures and latches this condition. 3 0 en_off_alert enables an alert if the hs operation is turned off by an operation that writes the swoff bit high. this allows software override of the alert output an d turns on a p-channel fet controlled by alert. 4 0 clear clears the oc_alert and adc_alert st atus bits in the status regist er. these may immediately reset if the source of the alert has not been cleared or disabled with the other bits in this register. this bit self- clears to 0 after the status register bits have been cleared. table 10. alert_th register operations bit default function 7:0 ff the alert_th register sets the current level at which an al ert occurs. defaults to adc full scale. the alert_th 8-bit number corresponds to the top eight bits of the current channel data. table 11. control register operations bit default name function 0 0 swoff forces the alert pin to deassert. can be active only if the en_off_alert bit is high (see table 9).
adm1192 rev. 0 | page 14 of 20 read voltage and/or current data bytes the adm1192 can be set up to provide information in three different ways (see the write command byte section). depending on how the device is configured, the following data can be read out of the device after a conversion (or conversions). voltage and current readback the adm1192 digitizes both voltage and current. three bytes are read out of the device in the format shown in table 12 . table 12. voltage and current readback format byte contents b7 b6 b5 b4 b3 b2 b1 b0 1 voltage msbs v11 v10 v9 v8 v7 v6 v5 v4 2 current msbs i11 i10 i9 i8 i7 i6 i5 i4 3 lsbs v3 v2 v1 v0 i3 i2 i1 i0 voltage readback the adm1192 digitizes voltage only. two bytes are read out of the device in the format shown in table 13 . table 13. voltage only readback format byte contents b7 b6 b5 b4 b3 b2 b1 b0 1 voltage msbs v11 v10 v9 v8 v7 v6 v5 v4 2 voltage lsbs v3 v2 v1 v0 0 0 0 0 current readback the adm1192 digitizes current only. two bytes are read out of the device in the format shown in table 14 . table 14. current only readback format byte contents b7 b6 b5 b4 b3 b2 b1 b0 1 current msbs i11 i10 i9 i8 i7 i6 i5 i4 2 current lsbs i3 i2 i1 i0 0 0 0 0 the following series of events occurs when the master receives three bytes (voltage and current data) from the slave device: 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address, followed by the read bit (high). 3. the addressed slave device asserts an acknowledge on sda. 4. the master receives the first data byte. 5. the master asserts an acknowledge on sda. 6. the master receives the second data byte. 7. the master asserts an acknowledge on sda. 8. the master receives the third data byte. 9. the master asserts a no acknowledge on sda. 10. the master asserts a stop condition on sda, and the transaction ends. for cases where the master is reading voltage only or current only, only two data bytes are read. step 7 and step 8 are not required. s slave address ra data 1 data 2 np data 3 a a 12 345678910 05754-010 figure 24. three-byte read from adm1192 s slave address ra register address np register data a 12 34 56 78 05754-011 figure 25. two-byte read from adm1192 converting adc codes to voltage and current readings the following equations can be used to convert adc codes representing voltage and current from the adm1175 12-bit adc into actual voltage and current values. voltage = ( v fullscale /4096) code where: v fullscale = 6.65 (7:2 range) or 26.35 (14:1 range). code is the adc voltage code read from the device (bit v0 to bit v11). current = (( i fullscale /4096) code)/ sense resistor where: i fullscale = 105.84 mv. code is the adc current code read from the device (bit i0 to bit i11). read status register a single register of status data can also be read from the adm1192. 1. the master device asserts a start condition on sda. 2. the master sends the 7-bit slave address, followed by the read bit (high). 3. the addressed slave device asserts an acknowledge on sda. 4. the master receives the status byte. 5. the master asserts an acknowledge on sda. s slave address ra data 1 a 12 345 05754-012 figure 26. status read from adm1192 table 15 shows the adm1192 status registers in detail. note that bit 1, bit 3, and bit 5 are cleared by writing to bit 4 of the alert_en register (clear).
adm1192 rev. 0 | page 15 of 20 table 15. status byte operations bit name function 0 adc_oc an adc-based overcurrent comparison has been detected on the last three conversions. 1 adc_alert an adc-based overcurrent trip has occurred, which has caused the alert. cleared by writing to bit 4 of the alert_en register. 2 oc an overcurrent condition is present (that is, the output of the current sense amplif ier is greater than the voltage on the setv input). 3 oc_alert an overcurrent condition has caused th e alert block to latch a fault, and the alert output has asserted. cleared by writing to bit 4 of the alert_en register. 4 off_status set to 1 by writing to the swoff bit of the control register. 5 off_alert an alert has been caused by the swoff bit. cleared by writing to bit 4 of the alert_en register. alert output the alert output is an open-drain pin with 30 v tolerance. there are two uses for this output. overcurrent flag the alert pin can be connected to the general-purpose logic input of a controller. under normal operation, the adm1192 drives this output low. when an overcurrent condition occurs, the output asserts high. an external pull-up resistor should be used. r sense p = vi controller adm1192 sense vcc sda scl sda scl gnd alert clrb clrb adr timer 3.15v to 26 v setv alert 05754-013 figure 27. using the alert output as an interrupt implementing a basic hot swap circuit a basic p-channel fet hot swap circuit can be created. the alert output should be connected to the gate pin of a p-channel fet connected in series with the power path. a pull- up from gate to source ensures that the p-channel fet gate is pulled up and the device held off as soon as power is applied. when the adm1192 powers up, the gate is pulled low by the alert output. a capacitor on the timer pin determines the slew rate of the gate at turn-on. note that if a current fault occurs at any point in operation, the alert output asserts high, turning off the p-channel fet. r sense p-channel fet p = vi controller adm1192 sense vcc sda scl sda scl gnd alert clrb clrb adr timer 3.15v to 26 v setv 05754-014 figure 28. p-channel fet hot swap implementation setv pin the setv pin allows the user to adjust the current level that trips the alert output. the output of the current sense amplifier is compared with the voltage driven onto the setv pin. if the current sense amplifier output is higher than the setv voltage, the output of the comparator asserts. by driving a different voltage onto the setv pin, the adm1192 detects an overcurrent condition at a different current level, with a gain of 18. see figure 12 for an illustration of this relationship. adm1192 setv 1.3v alert current sense amplifier a alert 60a r sense i load applied voltage sense vcc timer comparator 05754-015 figure 29. setv operation
adm1192 rev. 0 | page 16 of 20 when the output of the setv comparator asserts, this tells the alert block to begin charging the external timer capacitor with a 60 a charging current. when the voltage on the timer capacitor reaches 1 v, the charging cycle is complete. the alert output then asserts (goes high). different values of timer capacitor generate different time delays between current faults occurring and the alert output asserting. when using the alert output to implement a hot swap circuit, the timer capacitor should be chosen to generate a large enough startup delay to allow the maximum inrush current to completely charge up the load without tripping an alert fault. kelvin sense resistor connection when using a low value sense resistor for high current measure- ment, the problem of parasitic series resistance can arise. the lead resistance can be a substantial fraction of the rated resistance, making the total resistance a function of lead length. this problem can be avoided by using a kelvin sense connection. this type of connection separates the current path through the resistor and the voltage drop across the resistor. figure 30 shows the correct way to connect the sense resistor between the vcc pin and the sense pin of the adm1192. sense resistor kelvin sense traces vcc sense adm1192 current flow from supply current flow to load 05754-016 figure 30. kelvin sense connections
adm1192 rev. 0 | page 17 of 20 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 31. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model temperature range package description package option branding ADM1192-1ARMZ-R7 1 ?40c to +85c 10-lead msop rm-10 m5m eval-adm1192ebz 1 evaluation board 1 z = pb-free part.
adm1192 rev. 0 | page 18 of 20 notes
adm1192 rev. 0 | page 19 of 20 notes
adm1192 rev. 0 | page 20 of 20 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d05754-0-9/06(0)

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